1. Field of the Invention
The present invention relates generally to integrated circuits (IC) and more specifically to a method and apparatus for providing tolerance to indeterminate states that may occur at the scan outputs during scan tests of circuits.
2. Related Art
Test apparatus to run diagnostic and or/functional tests are frequently used to test electronic circuits (including circuit boards, etc.). In a common scenario, electronic circuits in integrated form (integrated circuits or ICs) may be subjected to various tests after fabrication to verify compliance with stated functionality and specifications. Thus, integrated circuits containing digital circuitry may be tested by inputting a sequence (or sequences) of digital bit patterns (test vectors) to various digital elements within the IC, and observing (and analyzing) the corresponding outputs.
Scan test techniques are often used to test ICs. When an IC is operated in a test mode, various sequential elements (such as flip-flops) in the IC are connected in a sequence (i.e., the output of one element is connected as an input to the next element) referred to as a “scan chain”. Many of such scan chains may be present and operated in parallel in the IC being tested.
In a typical scan test scenario, a number of bits in a particular pattern of zeros and ones (“scan vector”) are sequentially (one bit at every clock cycle) loaded (scanned-in) into a scan chain through the first element of the scan chain. Once the scan chains are loaded with the corresponding scan in vector, the functional circuit portions (generally the combinatorial logic) of the IC are evaluated based on the scanned-in bits. The flip-flops (contained in the scan cell) are designed to latch the results of the evaluation, and the bits latched in the scan chains are sequentially scanned out (scan-out) (one bit at every clock cycle) through the last scan cell in each of the scan chains.
In a combinational scan technique, only a single evaluation is performed in the evaluation phase, whereas in a sequential scan technique multiple evaluations may be performed in successive clock cycles (of a test cycle), before starting the scan out operation. The scan-in and scan-out operations are generally referred to as scan operations. In a sequential scan test (where sequential logic is tested) scan chains are generally subjected to one or more test cycles, with one test cycle being determined by one complete scan through the chain.
Signature analysis is often employed to analyze test outputs, particularly when a large number of scan chains are present in a circuit. In an example scenario, the scan chain outputs are compressed and provided to a signature generator (for example, a Multiple Input Signature Register (MISR)). The signature generator generates a test signature representative of the scan chain outputs collected over several test cycles, and provides the same to an external equipment (tester) which analyzes the signature to detect faults. By using such signature analysis techniques, a smaller amount of data can be conveniently examined to determine the presence of defects.
One problem with testing of digital logic in such environments is that some of the outputs may be in an indeterminate (unknown) state. Such indeterminate states may occur, for example, due to one or more uninitialized logic elements in the circuit (IC) that is being tested, or due to timing effects that may occur due to high speed testing.
Such indeterminate states (also called X states) may cause a signature generator (such as an MISR) to enter into an invalid state, consequently rendering the scan chain signature meaningless. One prior testing approach addresses such a problem (of indeterminate states) by not using a signature generator in the test path. However, such an approach denies the various benefits of signature analysis and may not be desirable in several environments.
Accordingly, what is needed is a method and apparatus that is tolerant to indeterminate states that may occur during circuit testing, while meeting one or more of the requirements noted above.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.